FIG. 1 shows a conventional master-slave type delay locked loop (DLL) circuit. The circuit generally includes a master DLL circuit 102 coupled to a slave DLL circuit 108 through a replica bias generator circuit 104 to control the delay of a signal (IN), e.g., clock, pulse, or the like, applied to the slave circuit 108 and provide the signal (OUT) from the slave DLL delayed by a desired amount, as dictated by the master DLL circuit 102. Master and slave DLLs can be configured in a variety of different ways. For example, a master DLL (such as master DLL 102) may comprise a phase-frequency detector, a charge pump, a loop filter, and a programmable voltage controlled delay line (VCDL), coupled as is commonly known, to generate a clock with desired delay characteristics from an applied reference clock (Ref Clk) and a self-generated feedback clock (Feedback Clk). Likewise, a suitable slave DLL to work in cooperation with the master DLL may include its own VCDL, along with a phase interpolator for added granularity.
The replica bias generator circuit 104 generates a replica of a bias signal (internal to the master DLL) used to control the master DLL circuit's VCDL. This replica bias signal (Slave Bias) is provided to the slave VCDL to control the delay of the signal applied to the slave DLL 108 in accordance with the desired delay that is generated at the master DLL circuit 102. (Note that the bias generator or replica bias generator may actually be part of the master DLL, providing the bias signal to both the master and slave DLLs, or alternatively, as is shown in FIG. 1, it may be a separate circuit to replicate, or create a suitable derivation of, a bias signal generated from the master DLL circuit.
The slave DLL circuit will generally be located close to the master circuit. This allows the slave to replicate or program its delay cells in the delay line to mimic the master delay characteristics. The close proximity makes it easier to protect the voltage bias signals through shielding and prevents aggressors (such as clocks) from routing over them.
Master-slave DLLs are used in a variety of applications such as with a double data rate (DDR) memory interface where they are used to delay various control signals. For example, with contemporary DDR systems, they are used to delay strobes to be 90 degrees out of phase from data bits in order to optimize margins in the READ and WRITE paths. DDR channels typically include 64 data bits organized into eight separate 8-bit modules, with each module having its own strobe signal. Thus, eight separate master/slave DLL circuits are typically employed to provide these eight separate strobe signals. Ideally, they are controlled to be at the same delay relative to a common reference clock. Thus, even though a single master circuit can source several different slave DLLs if they are sufficiently close to the master DLL circuit, eight separate master-slave sets are typically used since slaves would usually be too far from a common master circuit. Unfortunately, this results in excess power consumption since each master may consume on the order of tens of mill-Watts of power. Accordingly, a new approach is desired.